The invention relates to fibre channel arbitrated loop protocols, and more particularly, to a system and method of efficiently transmitting packets from a single source node to multiple target nodes.
In a Fibre Channel Arbitrated Loop (FCAL) topology, the xe2x80x9cloopxe2x80x9d is a resource shared by all ports. An arbitration protocol provides controlled access to the loop by the individual ports (device nodes) connected thereto. This protocol ensures that information sent from one port does not interfere with information sent from a different port. This is achieved by ensuring that only one port xe2x80x9cownsxe2x80x9d the loop at any time.
Before a source port can establish a loop circuit with one another port and begin frame transmission, the source port must arbitrate for access to the loop and win the arbitration. If more than one port requires access to the loop at the same time, each port arbitrates and the protocol determines which port wins the arbitration. Ports that fail to win arbitration may continue to arbitrate in order to win arbitration after the current loop circuit closes.
The above arbitration protocol resolves simultaneous arbitration requests based on each port""s loop address. Each loop address has an associated fixed priority that determines which port wins arbitration. If the higher-priority ports were allowed to arbitrate whenever they wanted, lower-priority ports might not be able to gain access to the loop at all. To prevent higher-priority ports from monopolizing access to the loop, the arbitration protocol uses xe2x80x9caccess fairnessxe2x80x9d rules. These access fairness rules establish an access fairness window during the period when multiple ports are arbitrating. During this window, each port observing access fairness is limited to win arbitration one time. Once a port has won arbitration, it must wait until a new access fairness window begins before it can arbitrate again. When all ports that are arbitrating during the current window have won arbitration, the access fairness window is reset and ports that were waiting can begin arbitrating if they require the loop. Ports that observe access fairness are called xe2x80x9cfair portsxe2x80x9d. Those that do not are called xe2x80x9cunfair portsxe2x80x9d. The decision of whether to behave fairly or unfairly is left to the system designer and may be fixed or dynamically changeable, depending on the workload. Some applications may benefit by allowing one or more ports to be unfair while requiring the remainder to observe access fairness.
After a port has won arbitration, a xe2x80x9cloop circuitxe2x80x9d is established with another port. The loop circuit is a logical connection between two ports conditioned for frame transmission and reception with each other. Other ports on the loop are either idle and monitoring the loop, or require accesses of their own and are arbitrating for access once the current loop circuit is closed. When the ports have completed their frame transmission, the loop circuit is closed and the loop is made available for use by other ports.
At the present, a transfer protocol is used to improve the efficiency of access fairness in a loop under certain circumstances. The transfer protocol includes rules for performing a xe2x80x9ctransfer operationxe2x80x9d whereby a current owner of the loop (i.e., the xe2x80x9cfairxe2x80x9d port that won arbitration) may close a currently open loop circuit (without relinquishing control of the loop and rearbitrating) to establish a new loop circuit with a different device. This might be desirable, for example, when a device wishes to have a file copied to multiple destination devices on the loop. A transfer operation thus allows ports with frames for multiple destinations to transmit those frames in a succession of loop circuits during a single loop ownership. This greatly reduces the overhead associated with arbitration since a current owner of the loop does not have to rearbitrate for access to the loop.
A transfer operation can occur regardless of whether the current owner of the loop won arbitration fairly or unfairly. Thus it makes sense that the transfer operation rules for unfair ports allow the current owner to ignore any arbitrating port. A fair port, on the other hand, by definition, must behave fairly. Consequently, any new transfer operation is ignored and control is relinquished to the winning arbitrating port. Thus, a fair port cannot take advantage of the improved frame transmission efficiencies of the transfer protocol if another port is arbitrating.
The inventors have found that by allowing a fair port to sometimes behave unfairly substantial performance improvements can be realized.
In some known FCAL implementations, a loop may selectively choose to be fair or unfair. In such cases, the decision to be fair or unfair is controlled by firmware or hardware located at the port and may be altered dynamically as conditions dictate. This allows for a loop port to dynamically assess frame transmission activity and respond by behaving fairly during periods of normal activity, but switch to unfair behavior during periods of peak activity. None of these implementations, however, suggest making a fair port (i.e., a port that has won arbitration fairly) behave unfairly. Instead, a port is designated as either fair or unfair before arbitrating and maintains that function for the entirety of its loop tenancy.
The invention relates to a method whereby a fair port in a Fibre Channel Arbitrated Loop behaves unfairly during portions of its loop tenancy and behaves fairly during other portions. In a preferred implementation, the fair port establishes a first loop circuit with an initial destination port. Before relinquishing control of the loop to an arbitrating port, the fair port establishes one or more subsequent loop circuits with other destination ports. Loop circuits are established in sequence without the fair port relinquishing control of the loop and rearbitrating. This continues until (1) the fair port establishes a loop circuit with every destination port to which it desires to exchange information; (2) a fixed time period has lapsed; and/or (3) a predefined maximum number of loop circuits are established.
The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention will be apparent from the description and drawings, and from the claims.